1. Field of the Invention
The present invention relates to high density, integrated circuit memory devices including flat cell ROM, and more particularly to structures for coupling banks of memory cells to array bit lines in which there are a plurality of columns of memory cells sharing each array bit line.
2. Description of Related Art
High-density integrated circuit memory designs often have an architecture that includes array bit lines, often called global bit lines, that extend across an array, and a number of shorter bank bit lines, often called local bit lines, that extend parallel to the array bit lines across a bank of memory cells in the array. For example, a bank bit line may extend across 32, 64 or 128 rows of memory cells in an array. Bank bit lines are typically implemented as diffusion regions in the substrate of the integrated circuit, and act as a source or drain for the memory cells to which they are coupled. The array bit lines are typically implemented as metal lines which extend over the array. Metal to diffusion contacts act as connection points for coupling the bank bit lines to the array bit lines. Bank select circuits are operated to connect a bank bit line to an array bit line in order to access a given memory cell on the bank bit line.
In the design of the bank select circuits, a number of factors is involved. The number of transistors through which the cell current must past through before connection with the array bit line affects the speed of operation of the device. The flexibility by which a given bank bit line may be coupled to one or more array bit lines affects the manner in which the individual cells may be accessed. Also, the design of the bank select circuits has a direct impact on the layout of the memory array. The bank select circuitry also determines whether a given bank bit line may be connected to ground or to a sense amplifier through array bit lines which may be dedicated to one or the other. Finally, the bank select circuitry may also limit the number of columns of memory cells which may be simultaneously coupled to sense amplifiers for high-speed, page mode implementations.
The prior art in this field includes U.S. Pat. No. 5,241,497; U.S. Pat. No. 5,117,389; U.S. Pat. No. 5,392,233; U.S. Pat. No. 5,812,440; and U.S. Pat. No. 5,392,233; and a large number of other references. A review of the bank selection circuitry for these prior art patents shows deficiencies in density, sensing speed or sensing flexibility of the prior art.
In modern memory design, such as for high-density, flat cell mask ROM for which speed of access is critical, the flexibility of the bank select structure becomes more critical. The bank select structure must involve as few transistors in the sensing path as possible to insure highest speed access to the data. Furthermore, in some designs, the number of array bit lines dedicated to ground terminals is reduced, and the need to share a ground line by more than one sense amplifier has arisen. Thus, the bank select structure must support the use of multiple sense amplifiers with a shared ground line, flexibility in the selection of memory cells to be accessed, high speed operation, and other aspects of high-density memories.